Bridging the first and last mile
for automatic routing tool
The Challenge: Routing for chips with advanced process nodes faces high IO pin density, more complex design rules, and increased routing failure rates. These issues significantly impact chip quality and lengthen design cycles, placing a heavy burden on chip design companies.
Our Mission: Pulsaris AI is dedicated to developing complementary products that enhance EDA algorithms with integrated AI models. Our goal is to streamline the design process for advanced process chips, improve chip quality, and shorten design cycles, ultimately making the entire chip design workflow more efficient.
Our Solutions:
- Theseus (AI-Native Chip router): Theseus is an AI-native chip routing model that reimagines the entire routing flow—from global routing and track routing to detailed routing. It delivers higher-quality routing with stronger design-rule-violation (DRV) resolution, shorter wirelength, fewer vias, and improved timing and power, enabling faster design convergence with fewer routing and optimization iterations.
- The first learning-based agent for chip routing – Unlike traditional algorithmic routers that rely on hand-crafted heuristics and may become trapped in local optima, Theseus learns routing strategies that consider the broader impact of routing decisions and search for better overall solutions across multiple design objectives.
- Seamless integration into existing AI-assisted chip design flows – While Theseus is AI-native, it is also designed to integrate naturally into modern AI-driven EDA platforms. The production model will expose a compact set of user-controllable objective parameters that can shift the routing strategy toward timing optimization, DRV reduction, or a balanced trade-off between the two. By conditioning the routing model on these parameters, users—or an LLM-assisted AI platform—can dynamically steer the optimization objective without changing the underlying model. This combination of AI-native routing and controllable optimization enables Theseus to retain the flexibility traditionally provided by tunable routing parameters while taking advantage of learned routing intelligence. Because routing directly affects timing, power, routability, wirelength, via count, and overall PPA, better routing can translate directly into higher chip performance, faster design closure, and greater chip value.
- Oumuamua (for pre-routing bridge): Deployed before mainstream routing software starts, Oumuamua uses reconnaissance agents to scan the routing environment, remove unnecessary wire segments, and perform basic local routing tasks. By clearing environmental obstacles for the later routing tools, it greatly boosts routing success rates and improves overall quality.
- Performance: Current test results, based on publicly available CFET process data, show a 16% reduction in total wire length, a 13% decrease in via count, a 3% drop in power consumption, and a 90% reduction in Design Rule Violations (DRVs).
- Lyra (for post-routing bridge): Operates after the main routing process to further enhance the output from the routing software. It provides the final refinement to the design.
- Performance: Lyra can cut wire length or via count by an additional 5% to 10% while ensuring successful routing. Additionally, it can remove or significantly reduce Design Rule Violations (DRVs) left by the main routing tools.