Bridging the first and last mile
for automatic routing tool
The Challenge: Routing for chips with advanced process nodes faces high IO pin density, more complex design rules, and increased routing failure rates. These issues significantly impact chip quality and lengthen design cycles, placing a heavy burden on chip design companies.
Our Mission: Pulsaris AI is dedicated to developing complementary products that enhance EDA algorithms with integrated AI models. Our goal is to streamline the design process for advanced process chips, improve chip quality, and shorten design cycles, ultimately making the entire chip design workflow more efficient.
Our Solutions:
- Oumuamua (for pre-routing bridge): Deployed before mainstream routing software starts, Oumuamua uses reconnaissance agents to scan the routing environment, remove unnecessary wire segments, and perform basic local routing tasks. By clearing environmental obstacles for the later routing tools, it greatly boosts routing success rates and improves overall quality.
- Performance: Current test results, based on publicly available CFET process data, show a 16% reduction in total wire length, a 13% decrease in via count, a 3% drop in power consumption, and a 90% reduction in Design Rule Violations (DRVs).
- Lyra (for post-routing bridge): Operates after the main routing process to further enhance the output from the routing software. It provides the final refinement to the design.
- Performance: Lyra can cut wire length or via count by an additional 5% to 10% while ensuring successful routing. Additionally, it can remove or significantly reduce Design Rule Violations (DRVs) left by the main routing tools.